Excavating
Patent
1991-09-25
1994-10-18
Harvey, Jack B.
Excavating
371 221, 371 225, 324765, H03K 1920
Patent
active
053575229
ABSTRACT:
A test circuit 2 connected between a programmable "AND" memory array 1 and an Input/Output macrocell 3 in an erasable and programmable logic device, for testing the Input/Output macrocell, comprising, a plurality of bit lines connected to the programmable "AND" memory array and the Input/Output macrocell, a plurality of extra test lines connected to a plurality of exterior pins respectively, a plurality of EPROM(Erasable Programmable Read Only memory) transistors which the drain thereof is connected to the bit line and the gate thereof is connected to the extra test line, wherein the EPROM transistors corresponding to the number of the bit lines connected to one logic sum gate forming a logic sum data path within the Input/Output machrocell are connected to one extra test line, and the other EPROM transistors excepting said EPROM transistors are respectively connected to one bit line and one extra test line.
REFERENCES:
patent: 3958110 (1976-05-01), Hong et al.
patent: 4719599 (1988-01-01), Natsui et al.
patent: 4780628 (1988-10-01), Illman
patent: 4878209 (1989-10-01), Bassett et al.
patent: 4905191 (1990-02-01), Arai
patent: 5060198 (1991-10-01), Kowalski
Harvey Jack B.
Hyundai Electronics Co. Ltd.
Wachsman Hal D.
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