Floating point remainder generator for a math processor

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364748, G06F 750

Patent

active

053574559

ABSTRACT:
A hardware floating point remainder generator is disclosed for performing a remainder (REM) function by receiving two floating point numbers (X and Y), by generating the remainder of X/Y according to a series of radix 4 SRT non-restoring division cycles and at most one single bit restoring division step, and by delivering the remainder.

REFERENCES:
patent: 4939686 (1990-07-01), Fandrianto
patent: 4979142 (1990-12-01), Allen et al.
patent: 5128891 (1992-07-01), Lynch et al.
Algorithm for High Speed Shared Radix 4 Division and Radix 4 Squre-Root, J. Fandrianto, 1987, IEEE.

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