Method for forming a dual thickness dielectric floating gate mem

Details Method for forming a dual thickness dielectric floating gate mem Method for forming a dual thickness dielectric floating gate mem

1992-06-18

1994-06-28

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 52, 437977, H01L 2170

Patent

active

053246764

ABSTRACT:
A semiconductor integrated circuit device is disclosed having first and second conducting layers, with the first layer having a shape which enhances field emission tunneling off of the surface thereof. A dual thickness dielectric layer separates the conducting layers. When a potential difference is applied between the conducting layers, field emission tunneling occurs primarily through the thinner portion of the dielectric layer. A method for forming a semiconductor integrated circuit device comprises the steps of (a) forming a first conducting layer, (b) forming regions of enhanced field emission on said first conducting layer, (c) forming a second insulating layer on the first conducting layer, (d) forming a masking layer (e) undercutting the second insulating layer, (f) etching the first conducting layer according to the masking pattern, (g) forming a third insulating layer on all exposed surfaces of the first conducting layer, such that a resultant insulating layer has first and second regions of different thicknesses, and (h) forming a second conducting layer over said resultant insulating layer.

REFERENCES:
patent: 4486769 (1984-12-01), Simko
patent: 4774202 (1988-09-01), Pan et al.
patent: 5017505 (1991-05-01), Fujii et al.

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