Method of formation of vertical transistor

Details Method of formation of vertical transistor Method of formation of vertical transistor

1992-11-19

1994-06-28

Kunemund, Robert

Fishing, trapping, and vermin destroying

437913, 257329, 257330, H01L 21265

Patent

active

053246730

ABSTRACT:
A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.

REFERENCES:
patent: 4449285 (1984-05-01), Janes et al.
patent: 4530149 (1985-07-01), Jastrzebski et al.
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4902641 (1990-02-01), Koury, Jr.
patent: 4902641 (1990-02-01), Koury, Jr.
patent: 4937641 (1990-06-01), Sunami et al.
patent: 4975754 (1990-12-01), Ishiuchi et al.
patent: 5057896 (1991-10-01), Gotou
patent: 5087581 (1992-02-01), Rodder
patent: 5122848 (1992-06-01), Lee et al.
patent: 5136350 (1992-08-01), Itoh
patent: 5208172 (1993-05-01), Fitch et al.
patent: 5235189 (1993-08-01), Hayden et al.
"High Performance Characteristics in Trench Duel-Gate MOSFET (TDMOS)", Tomohisa et al., IEEE Trans. on Elect. Dev., Sep. 1991, pp. 2121-2127.
"Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's," by H. Takato et al IEEE Transactions on Electronic Devices, vol. 38, No. 3, Mar. 1991, pp. 573-577.
"VMOS: High-Speed TLL Compatible MOS Logic" T. J. Rodgers et al., Journal of Solid State Circuit, vol. SC-9, No. 5, Oct. 1974.

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