Symmetrical programmable logic array

Details Symmetrical programmable logic array Symmetrical programmable logic array

1981-06-22

1984-02-14

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307247R, 307303, 357 45, H03K 19177

Patent

active

044319282

ABSTRACT:
A programmable logic array is provided by symmetrically arraying drivers around the periphery of a substrate. These drivers are essentially OR/NOR gates having latched complementary outputs. The latched complementary outputs enable these logic gates to be implemented into flip-flop elements, and the complementary outputs allow these logic gates to be implemented into AND logic gates. Selectable feedback paths are also provided to add greater flexibility to the programmable logic array. Altogether, the symmetrical logic array provides a simple one-to-one representation of most logic designs to form a universal logic design board in the form of a random logic or programmable state machine.

REFERENCES:
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patent: 4034356 (1977-06-01), Howley et al.
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4267463 (1981-05-01), Mayumi
patent: 4348737 (1982-09-01), Cukier et al.
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Mass., Oct. 1980, pp. 79-82.
Greenspan et al., "Merged AND/OR Array PLA Using Double Polysilicon FET Process", IBM T.D.B., vol. 23, No. 6, 11-1980, pp. 2189-2191.

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