Flip-flop in current mode logic controlled by a transfer clock w

Details Flip-flop in current mode logic controlled by a transfer clock w Flip-flop in current mode logic controlled by a transfer clock w

1982-11-03

1985-07-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307289, 307272A, 307272R, 307467, H03K 323, H03K 1986, H03K 313, H03K 193

Patent

active

045324409

ABSTRACT:
In order to avoid noise pulses which occur at the end of a clock pulse given a low signal level at the output of a clock-controlled flip-flop in ECL technology, an auxiliary current which is small in comparison to the primary current is supplied to a differential amplifier which is in a currentless condition during a clock pulse. As a result, the differential amplifier can be set to the respectively correct switch state before the end of the clock pulse.

REFERENCES:
patent: 3440449 (1969-04-01), Priel et al.
patent: 4359647 (1982-11-01), Trinkl
patent: 4408134 (1983-10-01), Allen

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