Minimal mask process for manufacturing insulated-gate semiconduc

Details Minimal mask process for manufacturing insulated-gate semiconduc Minimal mask process for manufacturing insulated-gate semiconduc

1982-08-09

1984-02-14

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29579, 29580, 29576B, 148187, H01L 21265

Patent

active

044307926

ABSTRACT:
Processes for manufacturing insulated-gate semiconductor devices such as MOSFETs wherein the source and base regions and the source-to-base ohmic short are formed employing self-aligned masking techniques are disclosed. In the exemplary case of a MOSFET, the processes begin with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. Through subsequent masking and etching steps, channels are etched through the polysilicon gate layer at least to the drain region. The un-etched portions define polysilicon gate electrodes spaced along the drain region. A two-stage polysilicon etch procedure is disclosed. An initial etch step produces relatively narrow channels. Unetched portions of the polysilicon layer are then used as masks to form a shorting extension of the device base region, preferably by ion implantation. In a subsequent lateral etch step, previously un-etched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures extending upwardly from and spaced along the principal surface. MOSFET source and base regions are then formed, preferably by vertical ion implantation, employing the polysilicon gate electrode structures as masks. Appropriate electrode metallization is applied.

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