Efficient interrupt control apparatus with a common interrupt co

Details Efficient interrupt control apparatus with a common interrupt co Efficient interrupt control apparatus with a common interrupt co

1995-06-12

1996-10-22

Ray, Gopal C.

395733, G06F 946

Patent

active

055686435

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to an interrupt control method and apparatus, more particularly relates to an interrupt control method and apparatus for a computer such as a simple small-sized computer like an RISC (Reduced Instruction Set Computer) which does not have a dedicated advanced interrupt processing circuit in the computer itself, but performs common interrupt processing on a plurality of divided interrupt input signals using a simple circuit provided at the outside of the computer and to an interrupt processing program run by that computer.


BACKGROUND ART

In recent years, much use has been made of work stations or image processing systems using simple small-sized computers, for example, RISCs.
An RISC is a computer which is designed to execute at a high speed the fundamental (basic) instructions used most frequently on the machine language level of the computer, for example, the store instructions, load instructions, etc. for the memory and registers. An RISC usually has an arithmetic processing circuit of a pipeline construction and is designed to execute the instructions in the same operating cycle to enhance to the maximum the performance of the pipeline construction arithmetic processing circuit.
Due to the above characteristics, an RISC is usually constituted by a much smaller number of circuit elements compared with a usual microprocessor or CISC (Complicated Instruction Set Computer) used for an apparatus of about the same size. Portions for realizing functions that are not necessarily required, but are provided by usual microprocessors are eliminated as much as possible.
For example, the RISC R3000 of the MIPS Co. has eight interrupt input terminals, but performs common interrupt processing on the interrupt input signals input to the interrupt input terminals by a single interrupt processing program. That is, no matter which interrupt input terminal an interrupt input signal is supplied to, a common interrupt processing program is executed for the interrupt input signal.
Some such RISCs do not provide the interrupt processing function for individual interrupt input terminals which had been provided even by 8-bit microprocessors, for example, the Z80 provided by the Zilog Co.
Accordingly, when such an RISC was used, it suffers from the disadvantage that when interrupt input signals are supplied to a plurality of interrupt input terminals, it is not possible to automatically activate the interrupt processing programs for the individual interrupt input terminals.
Furthermore, when a plurality of such interrupt input signals, for example, interrupt input signals from the peripheral circuits of the RISC, such as the DMA controller, serial communication device, etc. are multiplexed, it suffers from the disadvantage that the interrupt control for activating the interrupt processing programs is even more difficult.


DISCLOSURE OF INVENTION

The present invention has as its object to overcome the above-mentioned disadvantage and provide an interrupt control method and apparatus which enable efficient interrupt processing control for a plurality of interrupt input signals in a small-sized computer like an RISC which does not have a complex interrupt processing circuit constituted to perform the same processing on the interrupt input signals input to a plurality of interrupt input terminals.
Further, the present invention has as its object the provision of an interrupt control method and apparatus which enable modifications, expansions, etc. of the system to be flexibly dealt with.
According to the present invention, there is provided an interrupt control apparatus including: (a) storage means for storing an operating system, a common interrupt control program, interrupt processing programs for interrupt signals, and an interrupt table, (b) an address bus, (c) a data bus, (d) an arithmetic processing means connected through the address bus and the data bus to the storage means, having a plurality of interrupt input terminals, and having a status register for holding the status r

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