Method for fabricating stacked CMOS structures

Details Method for fabricating stacked CMOS structures Method for fabricating stacked CMOS structures

1984-09-28

1986-12-16

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29576J, 148188, 148191, 357 42, H01L 21385

Patent

active

046285890

ABSTRACT:
In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlayed p-channel device. To self-align the p-channel polycrystalline silicon device to the gate, a layer of polycrystalline silicon is deposited over the integrated circuit, followed by spinning on a layer of doped oxide which is then etched back to expose the polycrystalline silicon over the gate region. Thermally annealing the integrated circuit causes dopant from the doped layer to diffuse into the polycrystalline layer, thereby forming self-aligned source and drain structures.

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patent: 3899373 (1975-08-01), Antipov
patent: 4239559 (1980-12-01), Ito
patent: 4467518 (1984-08-01), Bansal et al.
patent: 4488348 (1984-12-01), Jolly
patent: 4502202 (1985-03-01), Malhi
patent: 4505024 (1985-03-01), Kawate et al.

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