Digital system error correction arrangement

Details Digital system error correction arrangement Digital system error correction arrangement

1979-12-31

1981-11-10

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 62, 371 30, 179 18BC, H04J 302

Patent

active

043002315

ABSTRACT:
There is disclosed an arrangement for removing error signals from a digital loop. A binary subtraction circuit is inserted in the loop and all signals passing through the circuit are reduced by a value which is dependent upon the magnitude of the accumulated signal. This arrangement serves to remove any accumulated DC offset bias from the digital signal.

REFERENCES:
patent: 3934091 (1976-01-01), Stidham
patent: 4002842 (1977-01-01), Meyr et al.
patent: 4048449 (1977-09-01), Natebusch
patent: 4049921 (1977-09-01), Zwack
Intel Corp. PCM Codec #2911, Jun. 1978, pp. 1-11.
Digital Processing of Signals, 1969, Discrete Linear Systems, pp. 1-11, by Bernard Gold et al.
IEEE Trans. on Communications, May 1978, A Twelve-Channel Digital Echo Canceler, vol. Com-26, No. 5, Duttweiller.

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