Processor having primary integer execution unit and supplemental

Details Processor having primary integer execution unit and supplemental Processor having primary integer execution unit and supplemental

1994-11-15

1997-10-07

Lim, Krisna

G06F 938

Patent

active

056757581

ABSTRACT:
The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.

REFERENCES:
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patent: 5430851 (1995-07-01), Hirata et al.
patent: 5434986 (1995-07-01), Kuslak et al.
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Sohi; "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers", IEEE Transaction on Computers, vol. 39, No. 3, 1990, pp. 349-359.

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