Online realignment of memory faults

Details Online realignment of memory faults Online realignment of memory faults

1982-06-16

1984-11-13

Atkinson, Charles E.

Excavating

365200, 371 2, 371 38, G06F 1110, G11C 2900

Patent

active

044830017

ABSTRACT:
A method is disclosed for operating a fault tolerant memory system which is provided with a fault alignment exclusion mechanism of the type disclosed in copending application Ser. No. 388,834. The method allows the assignment of a new permute vector to the fault alignment mechanism even though the memory is operating and storing user data. The method rearranges the data in the affected column by transferring data in one chip to another chip in the column through a buffer under the control of the old and new permute vectors. The transfer operation involves transferring the data at the same bit position from each chip in the column to a buffer under the control of the old permute vector and then transferring the data from the buffer to the same bit positions in other chips in the column determined by the new permute vector. The memory is then returned to the user for normal operation.

REFERENCES:
patent: 4074236 (1978-02-01), Ishida
patent: 4365318 (1982-12-01), Aichelmann, Jr. et al.
P. M. Ryan, Fault Realigment Through Grouping of Compatible Faulty Memory Chips, IBM Tech. Discl. Bulletin, vol. 26, No. 6, Nov. 1983, pp. 2753-2754.
Beausoleil, Maintenance for Memory with Error Correction, IBM Technical Disclosure Bulletin, vol. 11, No. 12, May 1969, pp. 1692-1693.
C. L. Chen, Fault Dispersion in Computer Memories, IBM Technical Disclosure Bulletin, vol. 25, No. 11A, Apr. 1983, pp. 5836-5838.

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