Patent
1996-08-19
1997-10-07
Beausoliel, Jr., Robert W.
G06F 1130
Patent
active
056757298
ABSTRACT:
The system of the present invention includes programmable logic to generate watchpoint traps which cause a branch to determined trap code and breakpoint signals which cause the stopping of the system dock. Furthermore, the system can measure system performance criteria. The logic is flexible and easy to program, but sophisticated in application to provide a variety of criteria that trigger on events which in turn increment the counters. In the preferred embodiment, the system includes two counters and trigger decode logic to increment the counters. Each counter is independently programmable to enable the user to determine such performance information as average latency, which is a combination of one counter counting the number of occurrences of a particular event and a second counter counting the duration of the events. Both counters can be programmed to measure on edges or levels of signals. In addition, the triggers can be used in a cascaded structure, wherein the first counter is used to generate a trigger which may be further qualified by the second counter. Using this implementation, a more flexible counting strategy is provided. Furthermore, by using the two counters in a cascaded fashion, the occurrence on one type of event can be used to monitor the occurrence of a second type of event in order to determine the occurrence of a combination of events. In addition, both watchpoint traps and breakpoint signals can be generated based upon the occurrence of a variety of events internal to the component and not easily accessible during execution by the user.
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Beausoliel, Jr. Robert W.
Elmore Stephen C.
Sun Microsystems Inc.
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