Error detection circuit

Details Error detection circuit Error detection circuit

1988-01-27

1989-07-25

Ruggiero, Joseph

Excavating

371 16, G06F 1130, G06F 1100

Patent

active

048520950

ABSTRACT:
An error detection circuit having a plurality of interconnected modules such as field replaceable units, each of the modules being driven by a system clock such that a failed module propagates errors to other modules before the system clock can be stopped. Each of the modules has at least one error checker circuit for generating an error checker signal when an error occurs. Each module includes an error trigger which is set responsive to the detection of an error checker signal, with each error trigger forming the stage of a counter whose count identifies the error trigger which was first set. The counter formed by the error triggers is preferably a Galois field counter which starts to count only upon the receipt of a non-zero impulse to any of its stages, and whose final count contains a unique value which identifies the source of the first non-zero impulse.

REFERENCES:
patent: 4139818 (1979-02-01), Schneider
patent: 4184630 (1980-01-01), Woodward et al.
patent: 4679195 (1987-07-01), Dewey
IBM J. Res. Devel., Tendolkar et al., "Automated Diagnostic Methodology for the IBM 3081 Processor Complex", vol. 26, No. 1, Jan. 1982, pp. 78-88.
IBM Technical Disclosure Bulletin, vol. 22, No. 1, Jun. 1979, pp. 255-257, "Algorithms for Increased Resolution of Field Replaceable Units", R. J. Kolvick, Jr.
IBM Technical Disclosure Bulletin, vol. 26, No. 11, Apr. 1984, pp. 6078-6079, "Error Sequence Tagging", W. P. Spraul.
IBM Technical Disclosure Bulletin, vol. 26, No. 11, Apr. 1984, pp. 6187-6188, "First Error Detection Circuit", R. H. Barsotti et al.

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