Programmable voltage offset circuit

Details Programmable voltage offset circuit Programmable voltage offset circuit

1988-10-11

1989-07-25

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365226, G11C 1134

Patent

active

048520632

ABSTRACT:
A programmable voltage offset circuit (PVOC) (1) comprises a temporary latch memory (7); a latch disable circuit (5) which selects that PVOC (1) among several such circuits which may be simultaneously present on the same semiconductor chip; a resistor array (3); and a programmable nonvolatile memory (37). The desired voltage offsets V(OFFSET)s are temporarily produced in an iterative manner using the latch memory (7). Quasi-permanent voltage offsets V(OFFSET)s are then programmed using the nonvolatile memories (37), each of which typically comprises an EPROM (39). Application of an avalanche voltage V(STORE) to a PFET (43) portion of the EPROM (39) causes the PFET (43) to avalanche, thereby selectively programming the nonvolatile memory (37), depending upon the status of a signal supplied from the latch memory (7).

REFERENCES:
patent: 4361847 (1982-11-01), Harari
patent: 4458348 (1984-07-01), Fukuda et al.
patent: 4541073 (1985-09-01), Brice et al.
patent: 4780750 (1988-10-01), Nolan et al.

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