Vector calculation circuit capable of rapidly carrying out vecto

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364736, G05F 752

Patent

active

048520403

ABSTRACT:
In a vector calculation circuit for use in a vector addition of first, second, and third vectors each of which is composed of an identical number to one another, a first adder circuit (26) comprises a carry save adder which carries out a carry save addition of a set of three components selected from the first through third vectors to produce a local sum and a carry collectively as a result of the carry save addition. The local sum and the carry is successively summed up by a second adder circuit (27) to produce a primary sum which forms an output vector. The primary sum may successively be sent back to the first adder circuit as the third vector. A selector circuit may be connected to the first adder circuit to select the first through third vectors and a fixed value of zero and to selectively add either two of the first through third vectors or three of them. Alternatively, a pair of selectors may be included to select either the first and the second vectors or the local sum and the carry.

REFERENCES:
patent: 3900723 (1975-08-01), Bethany et al.
patent: 4525796 (1985-06-01), Omoda et al.
patent: 4665479 (1987-05-01), Oinaga
patent: 4677547 (1987-06-01), Omoda et al.
patent: 4757444 (1988-07-01), Aoyama et al.
patent: 4777592 (1988-10-01), Yano

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