Semiconductor chip selection circuit having programmable level c

Details Semiconductor chip selection circuit having programmable level c Semiconductor chip selection circuit having programmable level c

1981-01-21

1984-11-13

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307471, 307463, H03K 19094, H03K 1921

Patent

active

044828225

ABSTRACT:
A chip selection circuit connected to select one of a plurality of semiconductor circuits including at least one memory circuit for addressing purposes, comprises first and second circuit elements directly coupled to each other at a point, at least one of the first and second circuit elements comprising an MOS transistor where the gate electrode is connected to the source electrode, a power source being applied between the first and second circuit elements by the application of a first voltage to the first circuit element and a second voltage to the second circuit element, and an exclusive AND gate circuit provided for receiving the output from the point and chip selection enabling signals to provide chip selection signals.

REFERENCES:
patent: 4069430 (1978-01-01), Masuda
patent: 4074238 (1978-02-01), Masuda
patent: 4084105 (1978-04-01), Teranishi et al.
patent: 4144587 (1979-03-01), Miyakawa et al.
patent: 4157480 (1979-06-01), Edwards
patent: 4208727 (1980-06-01), Redwine et al.
patent: 4323846 (1982-04-01), Haraszti
Richman, Characteristics and Operation of MOS Field-Effect Devices; McGraw-Hill, Inc.; 1967; pp. 114-118.
Williams et al., "Read-Only Storage Data Inversion for Speed Enhancement"; IBM Tech. Discl. Bull.; vol. 22, No. 8B, pp. 3793-3794; 1/18/80.
S. C. Lewis and J. E. Rock, "Noise Filter for FET Input Circuit", IBM Tech. Bull., vol. 22, No. 4, Sep. 1979, pp. 1407 to 1408.

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