Multiple input OR-AND circuit for FET logic

Details Multiple input OR-AND circuit for FET logic Multiple input OR-AND circuit for FET logic

1985-06-28

1987-12-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307475, 307443, 307279, 307558, H03K 19094, H03K 1716, H03K 508, H03K 326

Patent

active

047120223

ABSTRACT:
An OR-AND logic circuit includes a plurality of OR gates wherein each OR gate includes a plurality of source coupled FETs and the inputs to each OR gate are the control gates of the FETs. A logic node serves as the output for each OR gate. A unidirectional current conducting means, such as a Schottky diode, is connected to each output logic node of each OR gate. One terminal of each unidirectional current conducting means is connected to a common logic node. Current passing through a load means passes through the common logic node and is divided among the unidirectional current conducting means so that a logical AND function is provided at the common logic node with the logic condition at the output logic nodes of the OR gates serving as the inputs to the AND gate. Multiple levels of such OR-AND circuits can be provided with the AND output of one level serving as the input to an OR gate of the next stage.

REFERENCES:
patent: 4404480 (1983-09-01), Ransom et al.
Katsu, et al, A Source Coupled FET Logic--A New Current-Mode Approach to GaAs Logics, IEEE Transactions on Electron Devices, vol. ED-32, No. 6, Jun. 1985.
Shimano, et al, GaAs High Speed Digital ICs, ISSCC 83/Wed., Feb. 23, 1983.
Katsu, et al, A GaAs Monolithic Frequency Divider Using Source Coupled FET Logic, Electron Device Letters, vol. EDL-3, No. 8, Aug. 1982.

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