High speed counter

Details High speed counter High speed counter

1985-04-30

1987-01-13

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Particular transfer means

Including logic circuit

377111, 377123, H03K 2360, H03K 2362

Patent

active

046370382

ABSTRACT:
An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subsequent value decoder which has the function of determining the effect of lower order carry bits on higher order stages with a minimum of signal delay. The decoder includes the feature of using natural threshold FET devices in a transfer gate configuration to perform logical AND functions so as to minimize gate delays in decoding a carry condition for higher order stages. A selective up-counting or down-counting function is also disclosed.

REFERENCES:
patent: 3564218 (1971-02-01), Lay
patent: 3657557 (1972-04-01), Smith et al.
patent: 3906195 (1975-09-01), Maejima
patent: 3943378 (1976-03-01), Beutler
patent: 3992635 (1976-11-01), Suzuki et al.
patent: 4037085 (1977-07-01), Minorikawa
patent: 4464774 (1984-08-01), Jennings
patent: 4502014 (1985-02-01), Bismarck
patent: 4587665 (1986-05-01), Minakuchi

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