Enhanced CPU microbranching architecture

Details Enhanced CPU microbranching architecture Enhanced CPU microbranching architecture

1985-09-10

1987-01-13

Eng, David Y.

Boots, shoes, and leggings

G06F 922

Patent

active

046369430

ABSTRACT:
Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored and return to a desired line after a delayed call.

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