Patent
1985-07-15
1987-01-13
Edlow, Martin H.
357 49, 357 59, 357 41, H01L 2978, H01L 2710
Patent
active
046368345
ABSTRACT:
A method for making contact to a small area field effect transistor device is described. A monocrystalline semiconductor body having at least a surface region of a first conductivity is provided with a insulating layer over the surface region. A substantially horizontal first conductive layer is formed over the insulating layer. The insulating and first conductive layers are masked and etched to form openings in the layers to the semiconductor body where the source, drain and gate region of the device is desired to be formed. The openings have substantially vertical surfaces on the layered structure. A conformal, highly doped of a second conductivity conductive layer is formed over the openings having these substantially vertical surfaces and over the insulating and conductive layers. The conformal conductive layer is anisotropically etched to substantially remove the horizontal portions of the conformal layer while leaving the openings with a substantially vertical conformal conductive layer on the sides thereof. The semiconductor body with the layered structure thereon is heated at a suitable temperature to cause the dopant of a second conductivity to diffuse into the semiconductor body from the conformal conductive layer to form the source and drain regions and a first insulating layer upon the surface of the first conductive layer and the conformal conductive layer. A second insulating layer is formed over the vertical conformal conductive layer. Then a gate dielectric is formed upon the surface of the semiconductor body between the source and drain regions. Electrical contacts are made to the first conductive layer through the first insulator layer which effectively makes electrical contact to the source and drain regions through the horizontal conductive layer and the vertical conformal conductive layer.
REFERENCES:
patent: 3460007 (1969-08-01), Scott, Jr.
patent: 3484313 (1969-12-01), Tanchi et al.
patent: 3600651 (1971-08-01), Duncan
patent: 3664896 (1972-05-01), Duncan
patent: 3978515 (1976-08-01), Evans et al.
patent: 4209349 (1980-06-01), Ho et al.
patent: 4209350 (1980-06-01), Ho et al.
patent: 4234362 (1980-11-01), Riseman
patent: 4236294 (1980-12-01), Anantha et al.
patent: 4256514 (1981-03-01), Pogge
patent: 4309812 (1982-01-01), Horng et al.
patent: 4359816 (1982-11-01), Abbas et al.
patent: 4378627 (1983-04-01), Jambotkar
patent: 4379001 (1983-04-01), Sakai et al.
patent: 4400865 (1983-08-01), Goth et al.
patent: 4419809 (1983-12-01), Riseman
patent: 4419810 (1983-12-01), Riseman
patent: 4424621 (1984-01-01), Abbas et al.
patent: 4430791 (1984-02-01), Dockerty
patent: 4445267 (1984-05-01), Dida Moneda et al.
patent: 4464824 (1984-08-01), Dickman et al.
patent: 4470189 (1984-09-01), Roberts et al.
patent: 4507171 (1985-03-01), Bhatia et al.
Abbas et al., IBM TDB "Extending . . . Processing", Sep. 1977, vol. 20, No. 4, pp. 1376-1378.
Pogge et al., IBM TDB "Narrow . . . Method", Nov. 1976, vol. 19, No. 6, pp. 2057-2058.
Hunter et al., IEEE EDL vol. ED-2, No. 1, 1/81, pp. 4-6.
Jackson et al., IEDM 1979 Conference, pp. 58-61, "A Novel . . . Technique".
Ipri et al., IEEE Transactions on Electron Devices vol. ED-27, No. 7, 7/80, pp. 1275-1279.
Edlow Martin H.
Ellis William T.
International Business Machines - Corporation
Jackson, Jr. Jerome
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