Vertical Schottky barrier gate field-effect transistor in GaAs/G

Details Vertical Schottky barrier gate field-effect transistor in GaAs/G Vertical Schottky barrier gate field-effect transistor in GaAs/G

1984-06-05

1987-01-13

Edlow, Martin H.

357 234, 357 232, 357 15, 357 16, 357 55, H01L 2978

Patent

active

046368230

ABSTRACT:
High transconductance vertical FETs are produced in III-V epitaxially grown layers doped n, p and n, with the in-between submicron (0.15 .mu.m) layer serving as the FET channel. The layer on the drain side of the channel may be thicker (3 .mu.m) than on the source side (1.5 .mu.m). The structure is V-grooved to expose a nearly vertical surface that is Si implanted or regrown with graded n-type GaAs/GaAlAs before a gate contact is deposited on the vertical structure. An alternative to employ a heterostructure with GaAlAs layers for the source and drain, and GaAs for the channel layer. Graded GaAs/GaAlAs is then selectively regrown in the channel layer.

REFERENCES:
patent: 4219835 (1980-08-01), van Loon et al.
patent: 4466008 (1984-08-01), Beneking
Mok, et al., A V-Groove Schottky-Barrier FET for UHF Applications, IEEE Trans. Electron Devices, vol. ED-25, No. 10, Oct. 1978, pp. 1235-1240.
Salama, et al., Nonplanar Power Field-Effect Transistors, IEEE Trans. Electron Devices, vol. ED-25, No. 10, Oct. 1978, pp. 1222-1228.
Lisiak, et al., Optimization of Nonplanar Power MOS Transistors, IEEE Trans. Electron Devices, vol. ED-25, No. 10, Oct. 1978, pp. 1229-1234.
Tamer, et al., Numerical Comparison of DMOS, VMOS, and UMOS Power Transistors, IEEE Trans. Electron Devices, vol. ED-30, No. 1, Jan. 1983, pp. 73-76.

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