BIMOS memory sense amplifier

Details BIMOS memory sense amplifier BIMOS memory sense amplifier

1985-12-02

1987-01-13

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307355, 307491, 307495, H03K 524, G11C 706

Patent

active

046366652

ABSTRACT:
A BIMOS memory sense amplifier is provided having the low power dissipation and high noise immunity of CMOS devices while maintaining the high drive capability and switching speed associated with bipolar devices. A pair of differentially connected NPN transistors are coupled for receiving a first and a second bit current from the bit lines of a memory circuit. A MOS transistor circuit is coupled to the NPN transistors and is responsive to a differential output therefrom, for buffering two NPN push-pull output transistors.

REFERENCES:
patent: 3444472 (1969-05-01), Johnson
patent: 4267517 (1981-05-01), Iida et al.
patent: 4271394 (1981-06-01), Leidich
patent: 4375039 (1983-02-01), Yamauchi
patent: 4553053 (1985-11-01), Ong et al.
Schade, "A New Generation of MOS/Bipolar Operational Amplifiers"; _RCA Review; vol. 37, No. 3, pp. 404-424; 9/1976.
Miyamoto et al., "A High-Speed 64K CMOS RAM with Bipolar Sense _Amplifiers"; IEEE-JSSC; vol. SC-19, No. 5, pp. 557-563; 10/1984.
Lee et al., "BI-CMOS Technology for High-Performance VLSI _Circuits"; VLSI Design; 8/1984, pp. 98-100.
Bursky, Electronic Design, pp. 106-118; 10/4/1984.

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