Process for forming deep trench DRAMs with sub-groundrule gates

Details Process for forming deep trench DRAMs with sub-groundrule gates Process for forming deep trench DRAMs with sub-groundrule gates

1996-06-14

1997-10-07

Tsai, Jey

Fishing, trapping, and vermin destroying

437 60, 437919, 437203, H01L 218242

Patent

active

056747691

ABSTRACT:
A method of fabricating sub-GR gates in a deep trench DRAM cell. The method comprises depositing, removing, and selectively etching a plurality of layers which include sacrificial spacers, liners, masking, and resist layers of both semiconducting and non-semiconducting materials on a semiconductor substrate according to specific process flows designed to circumvent the problems associated with prior art sub-GR processes. The method represents an improvement on standard gate conductor processes and provides a device which achieves an up to now unachieved decoupling of channel doping and junction doping.

REFERENCES:
patent: 5073515 (1991-12-01), Roehl et al.
patent: 5106774 (1992-04-01), Hieda et al.
patent: 5429978 (1995-07-01), Lu et al.

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