Erasable programmable memory including buried diffusion source/d

Details Erasable programmable memory including buried diffusion source/d Erasable programmable memory including buried diffusion source/d

1987-12-09

1990-05-08

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 357 235, 437 43, G11C 1140

Patent

active

049244370

ABSTRACT:
An EEPROM cell and array of cells is disclosed having buried diffusion source/drain lines and buried diffusion erase lines. The cells further include coupling between the floating gate and control gate above the source/drain diffusion. The disclosed cell allows high packing density and operation at low voltages.

REFERENCES:
patent: 4405995 (1983-09-01), Shirai et al.
patent: 4453234 (1984-06-01), Uchida
patent: 4531203 (1985-07-01), Masuoka et al.
patent: 4561004 (1985-12-01), Kuo et al.
patent: 4750024 (1988-06-01), Schreck
Masuoka et al., "A 256K Flash EEPROM using Triple Polysilicon Technology", IEEE ISSCC, Feb. 14, 1985, Dig. of Tech. Papers, pp. 168-169, 335.

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