Low current semiconductor memory device

Details Low current semiconductor memory device Low current semiconductor memory device

1988-04-06

1992-04-14

Bowler, Alyssa H.

Static information storage and retrieval

Floating gate

Particular biasing

36518905, 36523008, 3652385, G11C 700, G11C 1600, G11C 11408

Patent

active

051053845

ABSTRACT:
Each column latch circuit latches a potential of each bit line and that of each control gate line before information is written in a memory cell. Thus, so-called page mode writing can be performed. A column latch circuit comprises two inverters of the same polarity and statically latches an input potential. As a result, chip size can be reduced without any leakage of an electric charge representing information. Reduction of operating current requirements is also achieved by the use of inverters of the same polarity in combination with control of at least one transistor within each of the two inverters.

REFERENCES:
patent: 4654826 (1987-03-01), Yamanouchi et al.
patent: 4694427 (1987-09-01), Miyamoto et al.
patent: 4710900 (1987-12-01), Higuchi
patent: 4733371 (1988-03-01), Terada et al.
patent: 4761764 (1988-08-01), Watanabe
patent: 4785424 (1988-11-01), Lin et al.
P.Suciu et al "A 64K EEPROM with Extended Temperature and Page Mode Operation", Digest of Technical Papers, 1985 IEEE International Solid-State Circuits Conference (Feb. 14, 1985): 170-172 and 336.

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