Method for the fabrication of dielectric isolated junction field

Details Method for the fabrication of dielectric isolated junction field Method for the fabrication of dielectric isolated junction field

1983-02-24

1984-11-13

Saba, W. G.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29576E, 29576W, 29577C, 148175, 156649, 357 22, 357 43, 357 49, 357 50, 357 56, H01L 2120, H01L 2176

Patent

active

044817070

ABSTRACT:
The process of fabricating a dielectrically isolated junction field effect transistor and a PNP transistor on a common substrate. An epitaxially layer is deposited on the base substrate to form the channel region of the junction field effect transistor. Impurities for the source and drain of the field effect transistor are diffused into the epitaxial layer. Impurities to form the gate are diffused into the epitaxially layer between the source and gate regions but separated therefrom. The PNP transistor which is dielectrically isolated from the field effect transistor by grooves, is formed by the diffusion into the base substrate of the respective impurities that form the base, collector and emitter regions of the PNP transistor.

REFERENCES:
patent: 3404450 (1968-10-01), Karcher
patent: 3412296 (1968-11-01), Grebene
patent: 3575646 (1971-04-01), Karcher
patent: 3755012 (1973-08-01), George et al.
patent: 3791024 (1974-02-01), Boleky
patent: 3876480 (1975-04-01), Davidsohn
patent: 3954522 (1976-05-01), Roberson
patent: 4255209 (1981-03-01), Morcom et al.
patent: 4286280 (1981-08-01), Sugawara

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