Pipelined instruction processor capable of reading dependent ope

Details Pipelined instruction processor capable of reading dependent ope Pipelined instruction processor capable of reading dependent ope

1984-12-28

1990-05-08

Zache, Raulfe B.

Boots, shoes, and leggings

364263, 3642318, 3642446, 3642624, 3642628, 3642613, 3642615, G06F 928, G06F 922, G06F 938

Patent

active

049243772

ABSTRACT:
Address calculation adders and a buffer storages are each independently provided for each operand of an instruction requiring two or more operands. In the translation instruction processing, the address calculations and operand fetch operations on the first and second operands are substantially asynchronously conducted. Consequently, the overhead that takes place one every n second operand fetch operations can be removed by independently and asynchronously performing the address calculations and operand fetch operations by use of a plurality of address adders. Moreover, the circuit for separating and obtaining a byte from the operand buffer can be dispensed with by adopting an operation procedure in which a byte of the first operand is fetched and is stored in temporary store means that supplies the address adder the data stored therein.

REFERENCES:
patent: 4130868 (1978-12-01), Heuer
patent: 4197578 (1980-04-01), Wada
patent: 4210960 (1980-07-01), Borgerson
patent: 4398245 (1983-08-01), Fujita
patent: 4467415 (1984-08-01), Ogawa
patent: 4556938 (1985-12-01), Parker
patent: 4594655 (1986-06-01), Hao et al.

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