Patent
1989-05-04
1990-05-08
Macon, Robert S.
357 43, 357 67, H01L 2348, H01L 2946, H01L 2954, H01L 2962
Patent
active
049242938
ABSTRACT:
A semiconductor integrated circuit device in which a wiring layer which supplies a predetermined operation voltage to an electronic circuit has a decreased parasitic impedance. The wiring layer is constituted by a first path and a second path that are connected in parallel between a connection pad and the electronic circuit, or a second wiring layer that constitutes an AC loop is formed close to the first wiring layer which supplies the operation voltage, or the above-mentioned two structures are employed in combination.
REFERENCES:
patent: 4314268 (1982-02-01), Yoshioka et al.
patent: 4437135 (1984-03-01), Ogata et al.
patent: 4607274 (1986-08-01), Yoshitake
Saito Yoshikazu
Yazawa Yoshiaki
Hitachi , Ltd.
Macon Robert S.
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