1989-04-20
1990-05-08
James, Andrew J.
357 234, 357 42, 357239, 357 2311, H01L 2978
Patent
active
049242776
ABSTRACT:
In a MIS transistor device, a gate electrode is formed on a first conductivity-type well region formed in a semiconductor substrate. By implanting impurities with the gate electrode and an element-isolating region made up of a field insulating film as a mask, an N-type diffusion layer having a higher impurity concentration than the first conductivity-type well region is formed on the sides of the gate electrode. A second conductivity-type diffusion layer of a first impurity concentration higher than the N-type diffusion layer is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on one side of the gate electrode. A second conductivity-type diffusion layer of a second high concentration is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on the other side of the gate electrode.
REFERENCES:
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4597824 (1986-07-01), Shinada et al.
patent: 4599789 (1986-07-01), Gasner
IEEE Transaction of Electron Devices, pp. 782-785 IEEM 1984 by K. Balasubramanyam et al.
IEEE Transactions on Electron Devices-vol. Ed-29 No. 4 pp. 611-618 Apr. 1982.
IEEE Transaction on Electron Devices pp. 242-245 IEDM 1985.
IEEE Transaction on Electron Devices vol. Ed-29 No. 4, Apr. 1982 pp. 590-596.
Fujii Tetsuo
Higuchi Yasushi
Yamane Hiroyuki
James Andrew J.
Nippondenso Co. Ltd.
Soltz David
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