Process of making an integrated circuit having a planar conducti

Details Process of making an integrated circuit having a planar conducti Process of making an integrated circuit having a planar conducti

1994-06-27

1996-01-02

Fourson, George

Fishing, trapping, and vermin destroying

437200, H01L 2144, H01L 2148

Patent

active

054808375

ABSTRACT:
An improved process for fabricating an integrated circuit is achieved by forming a planar conductive layer over closely spaced structures, such as gate electrode structures of field effect transistors (FET) and the electrically interconnecting word line structures of DRAM and SRAM chips. The planar conductive layer is then patterned by plasma etching to form the next level of electrical interconnecting bit lines, which makes contact to the source/drain of the FETs. The process involves the conformal deposition of a relatively thick polysilicon layer to fill the submicrometer spaces in the underlying structure. An etch back of the polysilicon and the deposition of a metal silicide is used to form an essentially planar conducting layer. This locally planar layer over submicrometer spaced features, with high aspect ratios, provides an ideal surface for exposing and developing distortion free and residue free submicrometer photoresist images required for Ultra Large Semiconductor Integration (ULSI).

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patent: 5200358 (1993-04-01), Bollinger et al.
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