Method of fabricating electronic circuitry unit containing stack

Details Method of fabricating electronic circuitry unit containing stack Method of fabricating electronic circuitry unit containing stack

1991-06-24

1992-04-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437208, H01L 2152, H01L 2156, H01L 2158, H01L 2160

Patent

active

051048205

ABSTRACT:
A process is disclosed which applies advanced concepts of Z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers, modification procedures are followed which create IC chips having second level metal conductors on top of passivation (which covers the original silicon and its aluminum or other metallization). The metal of the second level conductors is different from, and functions better for electrical conduction, than the metallization included in the IC circuitry. The modified chips are cut from the wafers, and then stacked to form multi-layer IC devices. A stack has one or more access planes. After stacking, and before applying metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the metallization formed on the access plane. Metal terminal pads are formed in contact with the terminals of the second level conductors on the stacked chips. The pads and terminals are formed of the same metallic material in order to maximize T-connection conducting efficiency.

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patent: 3657029 (1972-04-01), Fuller
patent: 4551629 (1985-11-01), Carson et al.
patent: 4597003 (1986-07-01), Aine et al.
patent: 4706166 (1987-11-01), Go
patent: 4880708 (1989-11-01), Sharma

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