Method of manufacture of high coupling ratio flash memory cell

Details Method of manufacture of high coupling ratio flash memory cell Method of manufacture of high coupling ratio flash memory cell

1994-07-15

1996-01-02

Fourson, George

Fishing, trapping, and vermin destroying

437 48, 257316, H01L 218747

Patent

active

054808197

ABSTRACT:
A process of fabricating an array of floating gate memory devices on a substrate comprises forming elongated spaced apart parallel ion implanted field implant regions in the substrate, forming elongated spaced apart parallel buried bit lines in the substrate orthogonally directed relative to the field implant regions, forming field oxide regions over the buried bit lines and field implant regions, and growing a silicon dioxide gate oxide layer having a thickness of from approximately 80 .ANG. to approximately 300 .ANG. between the field oxide regions, forming a plurality of first gate members from a first layer of polysilicon, the first gate members being disposed over the gate oxide layer, forming a layer of interpolysilicon dielectric over the first gate members having a thickness of approximately 150 .ANG., forming elongated second gate members from a second layer of polysilicon over the layer of interpolysilicon dielectric and over the first gate members, the second gate members extending generally perpendicular to buried bit lines.

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John P. Uyemura "Circuit Design for OMOS VLSI," pp. 66-69, 1992.

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