Method and apparatus for reducing jitter in a synchronous digita

Details Method and apparatus for reducing jitter in a synchronous digita Method and apparatus for reducing jitter in a synchronous digita

1986-06-10

1988-03-08

Buczinski, Stephen C.

Pulse or digital communications

Spread spectrum

Direct sequence

328 63, 328 74, 360 51, 375 14, H04L 2536, H03K 1726

Patent

active

047303476

ABSTRACT:
The method consists of using the recovered bit rate signal to define a time window which overlaps the beginning, but not the end of each jitter range in the version of the digital train intended for use by the bit rate recovery circuit. Those transitions in said version of the digital train which occur during said window are then delayed by a fixed delay of duration less than the maximum peak-to-peak amplitude of the jitter. Other transitions are not delayed. The apparatus shown is intended to operate with a binary version I of the digital train and with a recovered bit rate signal H which is symmetrical and rectangular in shape with a first one its levels defining a time window which extends over the second half of each period in the digital train. The apparatus is essentially constituted by a pulse generator (10) which transforms the transitions in the binary version I of the digital train into pulses of duration .tau. equal to one-half of the maximum peak-to-peak amplitude of the jitter, a first D-type register (11) delaying transitions in the recovered bit rate signal (8) so that they lie outside the pulses generated by the pulse generator (10), and a second D-type register (12) which delays transitions in the binary version I to lie outside the periods when the recovered bit rate signal having possibly delayed transitions (J) is at its first level. The apparatus is entirely constituted by logic circuits and is easy to integrate.

REFERENCES:
patent: 3057959 (1962-10-01), Rowe
patent: 3629712 (1971-12-01), Clark
patent: 3663883 (1972-05-01), Olso
patent: 4134073 (1979-01-01), MacGregor
patent: 4328587 (1982-05-01), Mizuno et al.

Affiliated with

Also associated with

Rating

Method and apparatus for reducing jitter in a synchronous digita does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for reducing jitter in a synchronous digita, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing jitter in a synchronous digita will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-234708