Programmable gate array with logic cells having symmetrical inpu

Details Programmable gate array with logic cells having symmetrical inpu Programmable gate array with logic cells having symmetrical inpu

1990-04-25

1993-07-27

Trans, Vincent N.

Boots, shoes, and leggings

364488, 364716, 34082583, 307465, H03K 17693, G06F 1520

Patent

active

052315886

ABSTRACT:
A configurable logic array includes an array of configurable logic cells arranged in columns and rows. A plurality of input/output cells are arranged around the perimeter of the array, and provide interfaces to input/output pads on the chip. A configurable interconnect structure includes vertical buses between the columns of configurable logic cells, and horizontal buses between the rows of configurable logic cells. Thus, each configurable logic cell in a subset of the array, has four adjacent buses in the interconnect structure. The configurable logic cells in this subset of the array include input structures, having programmable inputs connected to the buses on all four sides of the cell. Also, combinational logic connected to the input structure generates logic signals in response to the selected input signals. Finally, the configurable logic cells include output structures connected to the combinational logic, and having programmable outputs connected to the buses on all four sides of the cell.

REFERENCES:
patent: 4642487 (1987-02-01), Carter
patent: 4688072 (1987-08-01), Heath et al.
patent: 4706216 (1987-11-01), Carter
patent: 4713557 (1987-12-01), Carter
patent: 4758985 (1988-07-01), Carter
patent: 5036473 (1991-07-01), Butts et al.
patent: 5126950 (1992-06-01), Rees et al.
"The XC4000 Logic Cell Array Family-Data Book" Published by XILINX, 1991, pp. 1-64.
"The XC4000 Logic Cell Array Family-Technical Data" published by XILINX, 1990, pp. 1-53.
"On-Chip RAM and Hierarchical Routing Improve Programmable-Array Flexibility" by D. Burky, Electronic Design, Jul. 12, 1990, pp. 35-36.
"Third-Generation Architecture Boosts Speed and Density of Field-Programmable Gate Arrays" by P. Alfke, XILINX, Jun. 1990, pp. 1-12.
"The Programmable Gate Array Design Handbook"; 1st Ed.; published by XILINX, pp. 1-1 to 1-31.
"XC3000 Logic Cell Array Family"; published by XILINX; pp. 1-31 (FIG. 15b).

Affiliated with

Also associated with

Rating

Programmable gate array with logic cells having symmetrical inpu does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable gate array with logic cells having symmetrical inpu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable gate array with logic cells having symmetrical inpu will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2346848