Patent
1983-03-11
1986-02-04
James, Andrew J.
357 40, 357 68, H01L 2710
Patent
active
045689610
ABSTRACT:
A universal array of the type designed for automatic computer aided design of its customizing conductive layer is easily scaled to change the number of devices in the array. The array comprises an inner region having first direction extending rows of originally uncommitted device cells. Each row of cells is powered from first direction extending row power buses. These rows of cells are spaced apart in a second, perpendicular, direction by interleaved first type wiring corridors. The inner region is surrounded by an outer region including second type wiring corridors and peripheral cells. The second type wiring corridors space at least some peripheral cells from the inner region. The second type corridors include second-direction-extending inner-region-supplying power buses which connect to cell row power buses and wiring roadways spaced from the inner region by the inner buses. The wiring roadways are free of row power buses. The second type corridors are populated with tunnels which extend in the first direction only and underlie the roadways.
REFERENCES:
"Automated Design Procedures for VLSI" DELET-TR-78-2960-1, Jun. 1979, ERADCOM.
"Automated Design Procedures for VLSI", DELET-TR-78-2960-2, Feb. 1980, ERADCOM.
"Automated Design Procedures for VLSI", DELET-TR-78-2960-3, Jun. 1980, ERADCOM.
"Automated Design Procedures for VLSI", DELET-TR-78-2960-F, Mar. 1981, ERADCOM.
James Andrew J.
Ochis Robert
Prenty Mark
RCA Corporation
Tripoli Joseph S.
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