Inversion-mode insulated-gate gallium arsenide field-effect tran

Details Inversion-mode insulated-gate gallium arsenide field-effect tran Inversion-mode insulated-gate gallium arsenide field-effect tran

1984-01-03

1986-02-04

James, Andrew J.

357 232, 357 16, 357 22, H01L 2978, H01L 29161

Patent

active

045689580

ABSTRACT:
Inversion-mode insulated field-effect transistor structures are provided wherein a lightly-doped GaAs drift or drain region is combined with a gate-controlled channel structure comprising a film or layer of a semiconductor layer other than GaAs and within which inversion regions may more readily be formed. Suitable semiconductor materials for the gate-controlled channel structure are InP and Ga.sub.x In.sub.1-x As. Presently preferred is a Ga.sub.x In.sub.1-x As graded layer wherein x ranges from 1.0 to about 0.47.

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T. Kawakami et al., "InP/Al.sub.2 O.sub.3 n-Channel Inversion-Mode M.I.S.F.E.T.S Using Sulfur Diffused Source and Drain", Electronics Letters, vol. 15, No. 16, pp. 502-504 (8/2/79).
A. S. H. Liao et al., An In.sub.0.53 Ga.sub.0.47 As/Si.sub.3 N.sub.4 n-Channel Inversion Mode MISFET, IEEE Electron Device Letters, vol. EDL-2, No. 11, pp. 288-290, (1981).
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