Shift register using M.I.S. transistors of like polarity

Details Shift register using M.I.S. transistors of like polarity Shift register using M.I.S. transistors of like polarity

1997-03-28

2000-04-18

Wambach, Margaret R.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

377 79, 377 81, G11C 1900

Patent

active

06052426&

DESCRIPTION:

BRIEF SUMMARY
The subject of the present invention is a shift register which can contain just three M.I.S. transistors and enhancements to this circuit, and in particular allowing the selection of lines of pixels from a flat screen.
A flat liquid crystal screen is made up of a number of electro-optical cells arranged in rows and columns, each controlled by a switching device and containing two electrodes bordering a liquid crystal whose optical properties are modified as a function of the value of the field traversing it. The switching device/electrode/liquid crystal/counter-electrode assembly constitutes a "pixel" (standing for "picture element"). The addressing of these pixels by the peripheral control electronics is performed by way of rows (selection lines) which control the on and off state of the switching devices, and of columns (data lines) which transmit, when the switching device is on, a voltage to be applied to the terminals of the electrodes corresponding to the data signal to be displayed (gray scale).
The electrodes, the switching devices, the rows and columns are deposited and etched on the same substrate board, and they constitute the active matrix of the screen. Advantageously, the peripheral control circuits, that is to say the selection lines scanner which selects the horizontal lines to be displayed, and the circuits which control the data lines, are integrated onto the same substrate board containing the active matrix and are manufactured at the same time as the latter.
In a flat television or computer screen, the fact that the number of pixels is very large, that the spacing of the grid of these pixels is very small, thus limiting the space available in which to place the control circuit, and that a large number of selection lines and data lines are [sic] required, compels the use of the smallest and simplest possible control circuits so as to achieve a high degree of manufacturing efficiency. It may moreover be advantageous to use semiconductor devices as pixel switching devices, with the same conductivity type throughout the display.
Control of these semiconductor devices can be undertaken by lines addressed by one or more shift registers. A register structure such as that represented in FIG. 1 provides a partial response to the requirements stated in the previous paragraph. A stage 11 of a register contains six transistors Tp, Td, Ts, Tr, Tl and Tz, and is fed with two clock signals .PHI.1 and .PHI.2 at 14 and 15, as well as with two positive sources Vdd and one (relatively) negative source Vss. The operation of a shift register made up of such stages is described in detail in International Patent Application WO 92/15992 filed by Thomson LCD. This operation relies on the fact that the gate of the transistor Tl which controls the output 13 of the stage of the register is left floating, and that its potential therefore follows those of the clock and of the output through a capacitive effect. This is the "Boostrap" effect. This allows, at the desired moment, complete charging of the output 13 to the highest potential of the clock .PHI.1. The transistor Tp allows the gate of the transistor Tl to be precharged and allows the transistor Td to discharge this gate.
When the stage in question is not selected, its output 13 should remain at the potential Vss. However, the drain of the transistor Tl is permanently excited by the clock .PHI.1, and a consequence of the bootstrap effect described above is that, with each clock beat .PHI.1, the gate of the transistor Tl recovers around half the amplitude of the signals of .PHI.1 (typically about ten volts), and the transistor then becomes slightly passing. It is therefore necessary to switch on the transistor Tz in order to evacuate the charge from the node of the output 13 and force this node to the potential Vss. Likewise, the transistor Td must be kept on over the same period in order to keep the gate voltage of the transistor Tl permanently at the value Vss. The transistors Td and Tz must therefore have a control voltage which is always positive except wh

REFERENCES:
patent: 4035662 (1977-07-01), Kuo
patent: 4163291 (1979-07-01), Suzuki et al.
patent: 5122676 (1992-06-01), Stewart et al.
patent: 5410583 (1995-04-01), Weisbrod et al.
Patent Abstracts of Japan, vol. 9, No. 210 & Japanese Pat. 60-070599.

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