Method and apparatus for combining a direct-mapped cache and a m

Details Method and apparatus for combining a direct-mapped cache and a m Method and apparatus for combining a direct-mapped cache and a m

1994-08-11

1996-08-20

Robertson, David L.

395471, G06F 1314

Patent

active

055487424

ABSTRACT:
A two-way set-associative cache memory includes both a set array and a data array in one embodiment. The data array comprises multiple elements, each of which can contain a cache line. The set array comprises multiple sets, with each set in the set array corresponding to an element in the data array. Each set in the set array contains information which indicates whether an address received by the cache memory matches the cache line contained in its corresponding element of the data array. The information stored in each set includes a tag and a state. The tag contains a reference to one of the cache lines in the data array. If the tag of a particular set matches the address received by the cache memory, then the cache line associated with that particular set is the requested cache line. The state of a particular set indicates the number of cache lines mapped into that particular set.

REFERENCES:
patent: 4631660 (1986-12-01), Woffinden et al.
patent: 5228134 (1993-07-01), MacWilliams et al.
patent: 5257360 (1993-10-01), Schnizlein et al.
patent: 5325511 (1994-06-01), Collins et al.
patent: 5353425 (1994-10-01), Malany et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5367659 (1994-11-01), Iyengar et al.
patent: 5369753 (1994-11-01), Tipley
Anant Agarwal, et al., "Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches", Proceedings of the Annual International Symposium on Computer Architecture, May 1993, pp. 179-190.
Search Report from The U.K. Patent Office dated 1 Aug. 1995.
R. E. Kessler, et al., "Inexpensive Implementations of Set-Associativity", Proceedings of the 16th Annual International Symposium on Computer Architecture, May 1989, pp. 131-139.
Val Popescu, et al., "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. 10-13 and 63-73.
PCT International Search Report dated Mar. 5, 1996.

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