Boots – shoes – and leggings
Patent
1991-12-13
1997-05-27
Pan, Daniel H.
Boots, shoes, and leggings
395478, 395381, 364DIG1, 364DIG2, G06F 930, G06F 938, G06F 946
Patent
active
056341350
ABSTRACT:
A processor architecture comprises a priority processing unit (20), a priority memory (30), an instruction set memory (40), and an instruction execution unit (50). The priority processing unit (20) generates priority values and stores them in priority memory (30). Each priority value is associated with an instruction stored in instruction memory (40). Priority processing unit (20) causes the instruction associated with a particular priority value to be outputted to instruction execution unit (50).
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Donaldson Richard L.
Laws Gerald E.
McClure C. Alan
Pan Daniel H.
Texas Instruments Incorporated
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