Von Neumann system with harvard processor and instruction buffer

Details Von Neumann system with harvard processor and instruction buffer Von Neumann system with harvard processor and instruction buffer

1995-01-13

1998-01-06

Harrell, Robert B.

G06F 1200

Patent

active

057064660

ABSTRACT:
A hybrid Harvard/Von Neumann data processing system utilizes a Harvard architecture processor with a combined data/instruction memory. A dual-port random-access instruction buffer between memory and the processor provides much of the performance enhancement of an instruction cache when used with a RISC instruction set, but at a much lower cost. The resulting system serves as an entry-level computer system of a series of compatible computers, led at the high end by a Harvard processor with full data and instruction caches.

REFERENCES:
patent: 5301295 (1994-04-01), Leary et al.
Stephen B. Furber, "VLSI RISC Architecture and Organization" Marcel Dekker, Inc., 1989, pp. 2-5.
Brian Case, "AMD's 29030 Lynx Reduces System Cost "reprinted from Microprocessor Report, vol. 5, No. 9, May 15, 1991, in Understanding RISC Microprocessors, Ziff-Davis Press, Emeryville, CA, 1993, pp. 5-17-5-20.
Brian Case, "AMD'S 29200 Aims at Low-Cost Cost Laser Printers" reprinted fromMicroprocessor Report, vol. 5, No. 9, May 15, 1991, in Understanding RISC Microprocessors, Ziff-Davis Press, Emeryville, CA, 1993, pp. 5-21-5-24.

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