Method and apparatus overcoming delay introduced by instruction

Details Method and apparatus overcoming delay introduced by instruction Method and apparatus overcoming delay introduced by instruction

1994-12-23

1996-08-20

Lall, Parshotam S.

Boots, shoes, and leggings

395733, 364DIG1, G06F 930, G06F 946

Patent

active

055487360

ABSTRACT:
A pipeline operation control method and system in which, in the execution of successive first and second instructions, to avoid a pipeline disturbance, the second instruction is shifted from a calculating state to a special state as a final state that does not conflict with the final state of the first instruction when the first instruction has two or more calculating states immediately before the final state, and when the special state can be inserted as the final state of the second instruction and the calculating state of the second instruction is carried out within a single machine cycle, whereby the final state of the first instruction and the special state of the second instruction are carried out at the same time.

REFERENCES:
patent: 3949379 (1976-04-01), Ball
patent: 4656578 (1987-04-01), Chilinski et al.
patent: 4736288 (1988-04-01), Shintani et al.
patent: 4750112 (1988-06-01), Jones et al.
patent: 4782441 (1988-11-01), Inagami et al.
patent: 4903196 (1990-02-01), Pomerene et al.
patent: 4926323 (1990-05-01), Baror et al.
patent: 4942525 (1990-07-01), Shintani et al.
patent: 4965724 (1990-10-01), Utsumi et al.
patent: 4970641 (1990-11-01), Hester et al.
patent: 5202967 (1993-04-01), Matsuzaki
patent: 5212779 (1993-05-01), Saito
patent: 5222240 (1993-06-01), Patel
Smith et al, "Implementing Precise Interrupts in Pipelined Processors", IEEE, vol. 37, No. 5, May 1988, pp. 562-573.
"Programmable DSP Architecture", Lee, IEEE ASSP Magazine vol. 6, Iss 1, pp. 4-14, Jan. 1989.
"CPC--An Architecture Suited for Josephson and Pipelined Memory Machines", Shimizu et al., IEEE Compt, vol. 38, No. 6, Jun. 1989, pp. 825-832.
"Performance Comparison of Load/Store and Symetric Instruction Set Architectures" Alpert et al, IEEE Compt, pp. 172-181, May 1990.
"A Strategy for Avoiding Pipeline Interlock Delays in a Microprocessor", Yoshida et al, IEEE Compt., pp. 14-19, Sep. 1990.
Abraham et al., "Instruction Reorganization for a Variable-Length Pipelined Microprocessor", IEEE International Conference on Computer Design: VLSI in Computers & Processors, pp. 96-101, Oct. 1988.
"Roll-Back Interrupt Method for Out-of -Order Execution of System Programs", IBM Technical Disclosure Bulletin, vol. 32, No. 5A, Oct. 1989.
"Pipeline Processor Exception Control Mechanism", IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982.

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