Patent
1991-03-19
1998-01-06
Ellis, Richard L.
395588, 395590, 395595, 395563, G06F 900
Patent
active
057064601
ABSTRACT:
A variable vectored architecture digital computer provides real-time cont computations for a rocket control system by executing efficient variable-length instructions optimized for such an application by means of a microprogrammed processor and variable length fields within each instruction concept. A parallel architecture with two streams of commands is used with a new command structure. A new, more powerful instruction set was implemented to increase the throughput. Included in these new instructions are a series of block type moves which allow large amounts of data to be moved by loops within the microprogram instead of loops of firmware instructions which are fetched over and over again for each memory address. The new mechanization allows the firmware instruction fields to vary in length from 1 to 16 bits instead of the fixed 4 bit or 12 bit bytes found in the prior art.
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Craig Jack W.
Kancler H. C.
McBride C. W.
Ellis Richard L.
Hollis Darrell
The United States of America as represented by the Secretary of
Warsh Kenneth
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