Processor having a variable number of stages in a pipeline

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395800, G06F 938

Patent

active

057064598

ABSTRACT:
A processor, having a variable number of stages in a pipeline, splits, during a pipeline process, an instruction fetch stage or a memory access stage during an instruction fetch or a memory access of operand data for an external memory. This enables a simultaneous operation for both inputting instruction data and outputting an address for a fetch of the succeeding instruction data or a simultaneous operation for both inputting operand data and outputting an address for an access of the succeeding operand data.

REFERENCES:
patent: 4454578 (1984-06-01), Matsumoto et al.
patent: 4872111 (1989-10-01), Daberkow et al.
patent: 4912635 (1990-03-01), Nishimukai et al.
patent: 4967338 (1990-10-01), Kiyohara et al.

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