Digital signal regenerator arranged for fault location

Details Digital signal regenerator arranged for fault location Digital signal regenerator arranged for fault location

1986-05-27

1988-07-05

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

371 22, 375 4, H04B 346

Patent

active

047560053

ABSTRACT:
A digital signal regenerator, arranged for fault locating, receives a sequence of four-level signals representing first and second sequences of binary signals. When fault locating, the second sequence of binary signals is the same as the first sequence of binary signals but is delayed by n time slots. The received sequence of four-level signals is decoded into the first and second sequences of binary signals. Once decoded, the first sequence of binary signals is delayed by n time slots into a delayed first sequence of binary signals. The delayed first sequence of binary signals and the second sequence of binary signals are compared with each other. The comparator produces an error signal only when concurrent bits of the delayed first sequence of binary signals and of the second sequence of binary signals are different from one another.

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"GaAs Integrated Circuits for Error-Rate Measurement in High-Speed Digital Transmission Systems", IEEE Jrnl. Solid-State Circuits, C. A. Liechti et al., Aug. 1983, pp. 402-408.

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