Single chip processing system utilizing general cache and microc

Details Single chip processing system utilizing general cache and microc Single chip processing system utilizing general cache and microc

Filed on

1996-07-02

Date issued

1997-05-27

Examiner

Swann, Tod R.

Patent Class

Boots, shoes, and leggings

Other Related Categories

364DIG1, 364DIG2, 3642434, 36424342, 395450, G06F 1200, G06F 1300

Type

Patent

Status

active

Patent number

056341083

Description

ABSTRACT:
A microcode cache memory is provided on a processor chip for supplying frequently used microcode instruction words to a processor. A bank of multiple Tag-Status RAMs holds addresses of microcode words residing in a bank of Data RAMs. A state machine and a special Least Recently Used Random Access Memory (LRU RAM) operate to maintain the more frequently used words in the Data RAMs so that more hits occur to provide the requested word in one clock cycle. A 90 bit microcode word with 20 fields enables the processor to perform multiple functions simultaneously in parallel.

REFERENCES:
patent: 4439829 (1984-03-01), Tsiang
patent: 4719568 (1988-01-01), Carrubba et al.
patent: 4761733 (1988-08-01), McCrocklin et al.
patent: 5150469 (1992-09-01), Jouppi
patent: 5185878 (1993-02-01), Baror et al.
patent: 5210842 (1993-05-01), Sood

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