Prefetch memory system having next-instruction buffer which stor

Details Prefetch memory system having next-instruction buffer which stor Prefetch memory system having next-instruction buffer which stor

1986-01-27

1988-07-05

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 938

Patent

active

047559357

ABSTRACT:
A memory system (30) for storing and delivering instructions to a central processing unit (14) in a data processing system includes a main memory (32), a buffer memory (35) and a control unit (42). The main memory includes a series of memory slots (34), each memory slot storing one track. Each track consists of a sequential list of instructions which are executed in order unless a jump instruction is encountered. Each track ends with a jump instruction and begins with an instruction which is a target instruction of at least one jump instruction. The control unit copies each track into the buffer memory prior to delivering instructions from that track to the CPU. This buffer has a pointer (40) which specifies the next instruction in the buffer to be examined. If the instruction is a non-jump instruction, it is delivered to the CPU. If the instruction is a jump instruction which is to be executed, the track which begins with the target instruction specified in the jump instruction, if not already in the buffer, is loaded into the buffer.
Special jump instructions facilitate subroutine calls and interrupts by allowing jumps to be executed to target instructions which are not at the beginning of a track. A CPU/memory-system bus (48) includes signal lines under the control of the CPU, one or more of which may be used to control conditional jumps and signal interrupts to the memory system.

REFERENCES:
patent: 3245052 (1966-04-01), Lewin
patent: 3701980 (1972-10-01), Mundy
patent: 3906455 (1975-09-01), Houston et al.
patent: 3940741 (1976-02-01), Horikoshi et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4521850 (1985-06-01), Wilhite et al.
patent: 4594659 (1986-06-01), Guenthner et al.
patent: 4626988 (1986-12-01), George
James E. Smith et al., "Instruction Cach Replacement Policies and Organizations", IEEE Transactions on Computers, vol. C-34, No. 3, pp. 234-241, Mar. 1985.
James R. Goodman, "Using Cache Memory to Reduce Processor-Memory Traffic", Assn. for Computing Machinery, pp. 124-131, 1983.
Alan Jay Smith, "Cache Memories", Computing Surveys, vol. 14, No. 3, pp. 473-530, Sep. 1982.

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