Semiconductor memory device with read out data transmission bus

Details Semiconductor memory device with read out data transmission bus Semiconductor memory device with read out data transmission bus

1991-12-11

1996-08-20

Nguyen, Hoa T.

Excavating

G11C 2900

Patent

active

055485960

ABSTRACT:
The semiconductor memory device includes a read out data transmission line provided separately from a write data transmission line, a read out circuit including a differential amplifying circuit for amplifying a signal on the read out data transmission line, and a test circuit for comparing the signal potential on the read out data transmission line and a reference potential and detecting a defective bit. At the time of the normal mode, a memory cell of 1 bit is selected and the memory cell data of the selected 1 bit is transmitted to the read out data transmission line. At the time of the test mode, a plurality of memory cells are simultaneously selected and the simultaneously selected plurality of memory cell data are transmitted to the read out data transmission line. As a plurality of memory cells can be simultaneously tested using one pair of read out data transmission lines, the test time of the semiconductor memory device can be considerably reduced.

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Nakagome et al., "A 1.5V Circuit Technology for 64 Mb DRAMs", 1990 Symposium on VLSI Circuits, pp. 17-18.

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