Dynamic 1-of-2.sup.N logic encoding

Details Dynamic 1-of-2.sup.N logic encoding Dynamic 1-of-2.sup.N logic encoding

1996-03-01

1998-01-06

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular input circuit

377 81, 327407, 327410, 327333, G11C 1900

Patent

active

057063230

ABSTRACT:
A system of encoding a plurality of logic paths. A number of logic paths are subdivided into groups of N, N being greater than one. Each group of N logic paths is encoded such that an assertion of a given combination of the N logic paths results in a predetermined one out of 2.sup.N signal lines being asserted. Simultaneous assertion of more than one of the 2.sup.N signal lines is defined as an invalid state. A simultaneous non-assertion of all of the 2.sup.N signal lines enables precharging of the signal lines for dynamic operation. 1-of-2.sup.N encoding enables transmission of N variables by firing one out of N wires (rather than every wire, as in static logic, or one out of two wires, as in mousetrap logic). Signal degradation due to noise and coupling is reduced. In a multiplexer, 1-of-2.sup.N encoding reduces the load on the multiplexer's shift lines. Several 1-of-2.sup.N encoded multiplexers may be interconnected to form a self-timed dynamic shift register comprising one or more stages of tiered multiplexers. 1-of-2.sup.N encoding enables closer wire routings within such a shift register. Furthermore, 1-of-2.sup.N encoding can reduce the number of multiplexers required to implement a shift function.

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patent: 5243599 (1993-09-01), Barrett et al.
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patent: 5488318 (1996-01-01), Vajapey et al.
patent: 5534798 (1996-07-01), Phillips et al.

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