Patent
1987-09-14
1988-07-05
Carroll, J.
357 41, 357 45, 357 59, 357 71, H01L 2702, H01L 2710, H01L 2904, H01L 2934
Patent
active
047558644
ABSTRACT:
A semiconductor read only memory device is disclosed, which comprises a plurality of memory cells each including drain and source regions separately formed on a semiconductor substrate of p-conductivity type and a gate electrode insulatively disposed over the semiconductor substrate and extending between the drain and source regions. A poly-silicon layer containing an impurity of the p-conductivity type is formed such that it is contiguous to each drain region. A silicon nitride mask having electric insulation property and antioxidation property is formed selectively on the poly-silicon layer. The poly-silicon layer is oxidized selectively except for portions contiguous to the drain regions in the presence of the silicon nitride masks. An aluminum layer is selectively made in contact with the poly-silicon layer depending on the presence or absence of the silicon nitride layer.
REFERENCES:
patent: 4277881 (1981-07-01), Godejohn, Jr.
patent: 4305200 (1981-12-01), Fu et al.
patent: 4384345 (1983-05-01), Mikome
1979 Int'l Electron Devices Meeting, Technical Digest, "A New Self-Aligned Source/Drain Diffusion Technology from Selectively Oxidized Poly-Silicon" (Washington, D.C., Dec. 3-4-5, 1979).
Carroll J.
Kabushiki Kaisha Toshiba
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